This invention relates to a switching arrangement for a dc--dc converter and to a dc--dc converter including such a switching arrangement. The invention also relates to a switch component for use in such an arrangement or converter, the component being a switch device or a coupling and switch device.
U.S. Pat. No. 5,479,089 discloses a dc--dc converter having the general form shown in FIG. 1 of the accompanying diagrammatic drawings. A switching arrangement 46 has a switching signal input 3, a switch output 45, and a dc input 1 for receiving a dc input voltage of a given polarity relative to a common point 4. A switching signal source 18 which produces pulse-width-modulated switching pulses (a PWM controller) has its output connected to the switching signal input 3. The switch output 45 is connected to one end of an inductor 7 the other end of which is connected to a dc output 2. A capacitor 9 is connected between the dc output 2 and the common point 4.
In operation the arrangement 46 connects its switch output 45, and hence the one end of the inductor 7, alternately to the dc input 1 and to the common point 4 in response to the switching pulses applied to the switching signal input 3, thereby alternately causing the capacitor 9 to be charged from dc input 1 through inductor 7 and allowing energy stored in inductor 7 to be transferred to capacitor 9. The dc output 2 is coupled to a modulation signal input 19 of the PWM controller 18 to provide feedback to regulate the voltage at output 2. The converter therefore operates as a buck regulator.
As shown in FIG. 2 of the accompanying diagrammatic drawings, the switching arrangement 46 of the known converter includes first and second controllable semiconductor switches 5 and 6 respectively which are connected in series between the dc input 1 and the common point 4, with the first switch 5 connected to the dc input 1 and the second switch 6 connected to the common point 4. The connection 8 between the switches 5 and 6 is connected to the switch output 45. A first coupling 10 couples the switching signal input 3 to a control input 11 of the first switch 5, and a second coupling 12 couples the switching signal input 3 to a control input 25 of the second switch 6. The second coupling 12 has a threshold-responsive disable signal input 13 for disabling control of the switch 6 to its closed state when the voltage on this input has the given polarity (the polarity of the voltage at dc input 1) relative to a predetermined threshold value. The connection 8 between the switches 5 and 6 is connected to the disable signal input 13 via a clamp circuit comprising a resistor 14, a diode 15 connected in parallel with this resistor, and a Zener diode 16. The clamp circuit 14, 15, 16 is included to limit any positive voltage occurring at input 13 to a predetermined maximum value (assuming a positive supply voltage on dc input 1 relative to the common point 4). The first coupling also has a threshold-responsive disable signal input 17 for disabling control of the switch 5 to its closed state when the voltage on this input has the given polarity relative to a predetermined threshold value. Disable signal input 17 is connected to the control electrode 25 of switch 6.
The first coupling 10 comprises a two-input NOR gate 20, a two-input NOR gate 21, and a driver circuit 22, connected in cascade. The second input of NOR gate 20 is connected to ground and the second input of NOR gate 21 is connected to the disable signal input 17. NOR gate 20 operates as an inverter, as does NOR gate 21 when its second input, i.e. the voltage at disable signal input 17, is logic "0". (The logic "1" level has the aforesaid given polarity relative to the logic "0" level.) Thus, when the voltage at disable signal input 17 is logic "0", the application of a logic "1" level to switching signal input 3 by source 18 results in a logic "1" level at the output of NOR gate 21, and the application of a logic "0" level to switching signal input 3 by source 18 results in a logic "0" level at the output of NOR gate 21. On the other hand, when the voltage at disable signal input 17 is logic "1", NOR gate 21 produces a logic "0" level at its output, whatever the logic level is at switching signal input 3. Logic "1" and logic "0" levels at the output of NOR gate 21 cause driver circuit 22 to control switch 5 to its closed and opened states respectively.
The second coupling 12 comprises a two-input NOR gate 23 and a driver circuit 24, connected in cascade. The second input of NOR gate 23 is connected to the disable signal input 13. NOR gate 23 operates in a similar way to NOR gate 21, i.e. it operates as an inverter when its second input, i.e. the voltage at disable signal input 13, is logic "0". Thus, when the voltage at disable signal input 13 is logic "0", the application of logic "0" and "1" levels to switching signal input 3 by source 18 result in logic "1" and "0" levels respectively at the output of NOR gate 23. On the other hand, when the voltage at disable signal input 13 is logic "1", NOR gate 23 produces a logic "0" level at its output, whatever the logic level is at switching signal input 3. Similarly to driver circuit 22, logic "1" and logic "0" levels at the output of NOR gate 23 cause driver circuit 24 to control switch 6 to its closed and opened states respectively.
Assuming initially that the voltages at the disable signal inputs 13 and 17 are both logic "0", the operation of the circuit of FIG. 2 is conventional; the application of a switching signal consisting of alternating logic "0" and logic "1" levels to switching signal input 3 causes the driver circuits 22 and 24 to control the switches 5 and 6 to their open and closed states in an alternating manner and in antiphase. When switch 5 is closed and switch 6 is open capacitor 9 is charged from dc input 1 through inductor 7, energy also being stored in inductor 7 during this time. When switch 5 then opens and switch 6 then closes, the energy stored in the inductor continues to charge the capacitor 9.
The reason for the provision of the disable signal inputs 13 and 17 connected in the manner shown is that, in practice, the circuit is liable to operate in a less than ideal manner. More particularly there is liable to be some delay in the opening of the switches 5 and 6 in response to the relevant transitions in the switching signal applied to input 3, resulting in overlap of the periods during which the switches 5 and 6 (which may be constituted by field-effect transistors, FETs) are closed. It will be appreciated that such overlap can have disastrous consequences, as it will give rise to so-called "shoot-through currents" between the dc input 1 and the common point 4. The connection of the disable signal input 17 to the control input 25 of switch 6 ensures that gate 21 cannot produce a logic "1" in response to each transition of the switching signal at input 3 from logic "0" to logic "1", to thereby cause the switch 5 to close, until the voltage on the control input 25 of switch 6 has fallen below the logic "1" to logic "0" threshold level exhibited by the inputs of gate 21. (This situation corresponds to switch 6 being fully open.) Similarly, the connection of the disable signal input 13 to the connection 8 between switches 5 and 6 ensures that gate 23 cannot produce a logic "1" in response to each transition of the switching signal at input 3 from logic "1" to logic "0", to thereby cause the switch 6 to close, until the voltage on the connection 8 has fallen below the logic "1" to logic "0" threshold level exhibited by the inputs of gate 23. (This situation corresponds to switch 5 being fully open.) The converter therefore operates as an asynchronous-timed synchronous dc--dc converter.
In order to conserve energy modern PWM controllers may be arranged to go into `sleep-mode` under low load conditions, this being especially true for multi-phase controllers where one or more phases may shut off. "Sleep mode" in the context of the arrangement of FIG. 1 means that the source 18 will supply a logic "0" level to switching signal input 3 continuously. This will result in switch 5 being continuously open, isolating dc input 1 from dc output 2 as is required in such a situation. Switch 6 will initially close in the normal way when switch 5 opens, allowing the energy stored in inductor 7 to be transferred to capacitor 9. If it is assumed for example that the dc input voltage applied to input 1 is positive relative to common point 4, the voltage at connection 8 will be negative relative to common point 4, and decreasing in magnitude towards zero, when this happens due to the finite closed resistance of switch 6, so that the voltage at the disable signal input will also be negative but decreasing in magnitude towards zero, allowing switch 6 to be maintained in a closed state. When the energy in inductor 7 has been fully transferred, the voltage at connection 8 becomes zero and capacitor 9 starts to discharge through the inductor 7 and the closed switch 6. The current through the switch 6 changes sign when this happens, and starts to increase in the opposite direction, causing the voltage at the connection 8 to become increasingly positive. However, this increasing positive voltage will not normally exceed the logic "0" to logic "1" threshold level exhibited by the inputs of gate 23, or at least will not do so until the discharge current becomes quite large, so that the output of gate 23 remains at logic "1", the switch 6 remains closed, and the capacitor 9 continues to discharge through the closed switch 6, draining the energy stored in this capacitor.
Similar discharge of the capacitor 9 through the switch 6 occurs if the converter operates in discontinuous mode, i.e. if the mark-to-space ratio of the logic "1" switching pulses applied to the input 3 is sufficiently small and/or the inductance of the inductor 7 is sufficiently small that the energy stored in the inductor 7 becomes completely transferred to the capacitor 9 before each closure of switch 5. Each time the energy in the inductor becomes completely transferred the capacitor 9 starts to discharge through switch 6, and this discharge continues until the switch 5 closes once again or the discharge current becomes so large that the voltage on connection 8 exceeds the logic "0" to logic "1" threshold level exhibited by the inputs of gate 23. This obviously reduces the efficiency of the converter.